As memory chips become larger, the testing time required to verify that data is being correctly stored and read has increased, often at an exponentially growing rate. In dynamic wafer large-scale integration, wherein a relatively large number of memory chips on a single wafer are tested and then interconnected to provide an operative device when power is first applied (power up), the test time is particularly important.
Memory devices such as random access memories (RAMs) are commonly tested by applying signals of known logic levels to the memory cells and reading the signals out of the cells individually to determine whether they are of the proper level. In one commonly used test, a signal having a logic level of either one or zero is applied to one of the memory cells and signals of the opposite logic level are applied to the remaining cells. The signals are then read out of the cells individually and tested for the correct logic levels. This test must be repeated for each of the cells in the device, and the entire procedure is repeated with signals of the opposite levels. With a square array of n memory cells of a single bit, this test requires about 2.times.(3n+n.sup.2) memory cycles. For example, a 4096 bit RAM operating at a 1 microsecond rate would require a test time of over 30 seconds, and a 16,384 bit memory would take over 8 minutes to test. Thus, it can be seen that the test time for a single RAM chip can be excessive; and, when several hundred such chips on a wafer are tested sequentially, the test time is considerable.
With the introduction of larger scale chips, i.e. 4-meg bit memory cells, the test time becomes even more critical. The current industry standard is to set the test mode by doing a WCBR (CAS before RAS with WE low) and use the address inputs to determine into which test mode to go, and to RESET the test mode by doing either a CBR (CAS before RAS) or a RAS-only cycle. CAS is a COLUMN ADDRESS SELECT signal, and RAS is a ROW ADDRESS SELECT signal.
The 4-meg Dynamic Random Access Memory (DRAM) generation typically uses a WCBR (CAS before RAS with WE low) to put the device into test mode. This can create a problem since a less sophisticated device user might operate the device in this fashion even though it is an invalid timing scheme. This accidental misuse inadvertently activates the test mode when it is not desired.
In conjunction with the above signals, the activation of the test mode within an IC memory chip is done by the use of a supervoltage, at the normal power supply VDD, where the voltage pulse used is about 11 volts, in lieu of the normal 5 volts. The use of this supervoltage pulse is undesirable because stacked diodes must be used and they are very temperature dependent. Additionally, as IC chip gate oxides get thinner, the higher voltages create an oxide insulation breakdown risk reducing reliability.
It is thus an object of this invention to provide a test mode activation circuit that avoids the potential problem of inadvertent activation of the test mode by the IC chip user. It is a further object of this invention to eliminate the need for a supervoltage power supply pulse circuit.